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Specialist Study: Building Testability into FPGA & ASIC Designs

This paper discusses how the architecture for FPGAs and ASICs should be defined to improve the testability, quality, effort and hence cost of the verification activities.

By Matt Noonan, Project Manager, Phixos

Abstract

This case study explores the importance of improving testability in FPGA and ASIC designs to enhance verification activities in terms of quality, effort, and cost. In safety-critical industries, firmware within these designs often falls in a grey area between hardware and software engineering roles.

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