FPGA usage within high integrity systems is becoming both more popular and more complex. One of the challenges of putting an FPGA in a high integrity system is the cost of verifying its correct operation, and this is made significantly more difficult by the increasing complexity of FPGA applications. For a typical DO-254 Level A aerospace FPGA application, at least 50% of the overall effort and engineering budget is spent on verification activities. As design decisions are set in stone early in the development process, it is common to discover unexpected verification problems when it is too late to do anything about it. This paper seeks to explore and quantify the effect of various architectural and design structures of their ‘testability’ for FPGA systems in high integrity applications, as well as identifying test based mitigations for common problems. Using anonymised data from Phixos’s high integrity customers, a study of varied design structures has been analysed into a set of testability rules and a summary of their respective impact on the effort of verification.
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